Jianqiao Mo (莫剑桥) -- I am a PhD candidate in Electrical and Computer Engineering at New York University
(BAAHL), advised by
Brandon Reagen and
collaborating with
Siddharth Garg and Benedikt Bünz.
Before NYU, I received my B.S. from Nanjing
University, where I worked as an efficient neural network research intern advised by
Zhongfeng Wang.
My research advances data privacy and integrity through hardware-software co-design.
I build
efficient systems that make cryptographic privacy and integrity practical.
Privacy-Preserving Computation for End-to-End Data Privacy: I develop
specialized hardware systems to accelerate
privacy-preserving computation. My work includes accelerators for cryptography (e.g., homomorphic encryption), particularly
Garbled Circuits (GC)[1],
[2],
which enable accurate private ML inference.
Applying privacy-preserving computation to private inference.
Zero-Knowledge Proofs for Data Integrity: I develop efficient proof systems
and programmable hardware accelerators for zero-knowledge proofs (ZKPs). ZKPs verify data
integrity by proving the correctness of computations without revealing the underlying data.
zkPHIRE: A Programmable Accelerator for ZKPs over HIgh-degRee, Expressive Gates International Symposium on High-Performance Computer Architecture (HPCA), 2026
zkPHIRE provides programmable acceleration for zero-knowledge proofs using high-degree,
expressive gates.
MTU: The Multifunction Tree Unit for Accelerating Zero-Knowledge Proofs Hardware and Architectural Support for Security and Privacy (HASP), 2025
MTU accelerates common tree operations in zero-knowledge proof systems with a multifunction
hardware unit.
Need for zkSpeed: Accelerating HyperPlonk for Zero-Knowledge Proofs International Symposium on Computer Architecture (ISCA), 2025
zkSpeed accelerates HyperPlonk Protocol proof generation through hardware-software co-design for
zero-knowledge proof workloads.
HAAC: A Hardware-Software Co-Design to Accelerate Garbled Circuits International Symposium on Computer Architecture (ISCA), 2023
[ISCA slides/YouTube],
[DISCC]
HAAC combines a tailored compiler and memory architecture to accelerate Garbled Circuits (GC) Protocol for
data-oblivious, privacy-preserving computation.
ABLE implements and optimizes transformations between Boolean and arithmetic GC, enables the selection of an efficient mixed-circuit realization for privacy-preserving computation.
